A deterministic microkernel. No Linux. No libc. 4 dedicated CPU cores. Every byte of RAM, every CPU cycle, every hardware register — under your direct control.
Core architecture
- Core 0 — Kernel services + Network + Disk
- Cores 1-3 — User schedulers with preemptive 5ms quanta
- Each core gets 16MB private RAM
- 16 lock-free SPSC ring buffers for inter-core messaging
What's running
| Network | IP/TCP/UDP/ICMP/ARP/DNS — hardened, no fragmentation |
| Storage | SDHCI driver + WALFS append-only filesystem |
| Display | HDMI 1024×768 framebuffer + UART serial console |
| Compute | NEON/SIMD + DMA scatter-gather + QPU tensor dispatch |
| USB | xHCI host via RP1 — HID keyboard + mass storage |
| Security | EL2→EL1 boot, capsule isolation, capability-gated pipes |
Unified pipes
/ipc, /net, /fs, /hw — all domains mapped through capability-gated pipe adapters. Everything is a stream.
When you own every cycle, latency becomes a choice, not an accident.